The disclosure relates generally to three-dimensional (3D) integrated circuit (IC) structures, and more particularly, to 3D IC structures having improved power and thermal management.
To the inventor's knowledge, 3D ICs are a potential solution to traditional two-dimensional (2D) ICs to overcome the interconnect scaling barrier and improve performance. In 3D ICs, multiple dies are stacked together using vertical through silicon vias (TSVs) where longer wire connections and inter-die input/output (I/O) pads are eliminated, resulting in overall performance improvements, including faster and more power efficient inter-core communication across multiple silicon layers. FIG. 1 is a cross-sectional view of a current 3D IC structure 10 having dies A, B, C, and D stacked one on top of another on a substrate 20, each of the dies A, B, and C having one or more TSVs 40 for inter-die communication. FIG. 2 is a top view of the 3D IC structure of FIG. 1.
There are power and thermal management challenges with respect to 3D IC technology. When multiple dies are stacked together, the total power is the sum of the individual dies. The stacked dies and TSV resistance are added in series for power routing. This causes high current (I) and resistance (R) that can lead to a significant IR drop (i.e., voltage drop). To address the IR drop problem, a dense power network is required and additional bottom die areas are reserved for inter-die power supply—but this occupies significant routing resources and leads to routing congestion resulting in a large die area. The area penalty increases dramatically when the numbers of stacked dies are increased.
Furthermore, when multiple dies are stacked together, heat trapped between the die interfaces is difficult to dissipate through the dielectric layer. The increased temperature results in performance degradation and reliability problems. Expensive cooling systems (e.g., thermal vias and liquid microchannels) may then be required for proper heat dissipation.